Recently, as the speed and complexity of integrated circuits increase, a clock timing fluctuation (jitter) occurs due to noise or variations in a chip, thereby causing an operation error. Conventionally, a signal is extracted outside an integrated circuit, and the behavior of the signal is observed. However, while the operating frequency of an integrated circuit rises year by year, the operating frequency band of a board or package outside the integrated circuit does not follow this rising rate. This makes a high-speed operating clock inside an integrated circuit difficult to observe outside the integrated circuit. Also, if the clock is extracted outside the integrated circuit, a jitter occurring during the process of extracting the clock outside the integrated circuit is added to the jitter occurring inside the integrated circuit, so the internal jitter of the integrated circuit is difficult to accurately estimate. This increases the importance of a method of observing the internal operation of a chip by forming a phase difference observation circuit inside the chip.
A method that compares a clock to be measured with a reference clock and detects the phase difference as a jitter of the clock to be measured is widely known as a method of measuring a clock's jitter. In this method, the resolution of a phase difference measuring circuit that measures the phase difference between two signals determines the measurement performance.
A conventional method of measuring the phase difference between two signals is disclosed in reference 1 (Japanese Patent Laid-Open No. 2000-111587). In this method as shown in FIG. 21, the phase of a signal S0 to be measured is shifted by a plurality of delay elements 2201, and compared with the phase of a reference signal R0. If the signal S0 to be measured deviates from the reference signal R0 by time Tjit, a phase difference Tjit is input to a first phase comparator C0, and a phase difference Tjit−Ts (Ts is the delay of the delay element 2201) is input to a second phase comparator C1. The phase comparators C0, C1, . . . are circuits that output “1” when the phase difference is 0 or more, and “0” in other cases. Since the output result from a phase comparator CN for which Tjit−N×Ts is 0 or less becomes “0” for the first time, the value of N is found by observing this result. On the basis of this value, the phase difference Tjit can be measured to be approximately N×Ts.
Unfortunately, this method cannot achieve a resolution equal to or smaller than the delay Ts of the delay element 2201, and this makes high-performance jitter measurements difficult.
As a phase difference measuring device for solving this problem, a method proposed in reference 2 (Custom Integrated Circuit Conference, pp. 251, 2001) will be explained below. As shown in FIG. 22, a delay element having a delay time Ts and a delay element having a delay time Tr are used to form a phase difference conversion circuit 2301. First, the first phase difference conversion circuit 2301 shifts the phase difference between a reference signal R0 and a signal S0 to be measured by Td (=Ts−Tr), and the phase difference between S1 and R1 becomes Tjit−Td as shown in FIG. 23. Then, a second phase difference conversion circuit 2302 shifts the phase difference between R2 and S2 by Td (=Ts−Tr), and the phase difference between S2 and R2 becomes Tjit−2Td. Thus, signals are generated in each stage by shifting the phase difference between two signals by Td (=Ts−Tr). Subsequently, phase comparators C0, C1, . . . compare the phases of these outputs, and output the comparison results. The resolution of this phase difference measuring device is Td.
In this method, if a maximum jitter (a maximum value of the time difference Tjit between the reference signal R0 and the signal S0 to be measured) is m×Td (m is an integer), m phase difference conversion circuits 2301 must be cascaded to perform measurements, so a time of m×Tr is required from inputting of the two signals to outputting of the results (i.e., to arrival of the signals at the final stage). If this value increases, the number of times of measurements per unit time is limited, and the variations of the delay elements increase the error of the delay time until the signals arrive at the final stage, thereby decreasing the measurement accuracy.
A method of reducing the influence of the element variations as described above is proposed in reference 3 (IEEE International Solid-State circuits conference (ISSCC), pp. 170, 2000). This method randomly sets phase differences between input signals, and repetitively performs measurements, thereby obtaining a correlation between the output result and the input signal phase difference. If a difference from an ideal value is large, the method changes the delay of an element or the value of an offset adjusting circuit, and repetitively executes the random measurements, thereby reducing the variations.
Unfortunately, this method has the problems that, e.g., a random signal generating means is necessary, the repetitive measurements increase the measuring time, and an offset adjusting circuit changing algorithm having a high convergence is necessary.
Also, reference 4 (IEEE Journal of Solid-state circuits, pp. 1360, 1999) has proposed a method using a Delay-Locked-Loop (DLL) that reduces the influence of variations by controlling the delays of delay elements. This method has the problems that, e.g., a delay cell whose delay is controllable must be designed, the configuration must be changed if an input clock frequency changes, and the variation of each delay element cannot be controlled although the delay time of the whole phase difference measuring circuit is controllable.
Furthermore, it is difficult to adjust the offset of a flip-flop as shown in FIG. 24 used as a phase comparator. Therefore, reference 3 has also proposed a phase comparator as shown in FIG. 25 as an offset-adjustable phase comparator. However, this phase comparator requires a sync signal (clock) for driving a precharge terminal 2601 in addition to two signals (inputs 1 and 2) as objects of phase difference measurement, and the generation and distribution of the sync signal increase the complexity of design.